Silicon carbide (SiC) is a semiconductor material that is expected to be applied to next-generation low-loss power devices, etc., as it has a large bandgap than silicon (Si) and has desirable physical properties such as a high breakdown field strength. Silicon carbide has many polytypes such as cubic 3C—SiC and hexagonal 6H—SiC and 4H—SiC. One of these polytypes that is commonly used for producing a practical silicon carbide semiconductor device is 4H—SiC.
When producing a silicon carbide semiconductor device such as a metal-insulator-semiconductor field effect transistor (MISFET), a 4H—SiC substrate whose principal surface substantially coincides with the (0001) Si plane which is perpendicular to a crystal axis, the c-axis, is normally used. An epitaxial growth layer to be an active region of the silicon carbide semiconductor device is formed on the 4H—SiC substrate (hereinafter referred to simply as the “SiC substrate”). An impurity-doped layer whose conductivity type and carrier concentration are controlled depending on the type of the semiconductor device to be produced is formed by ion implantation, or the like, in a selected region of the epitaxial growth layer. The impurity-doped layer functions as a p-type body region (well region) 105 or an n+ source region in a MISFET, for example.
The structure of a MISFET using SiC (SiC-MISFET) is proposed in Patent Document No. 1, for example.
FIG. 8(a) is a schematic plan view showing a portion of a conventional vertical MISFET using SiC, and FIG. 8(b) is a cross-sectional view taken along line I-I′ of FIG. 8(a).
As can be seen from FIG. 8(a), a vertical MISFET 400 includes a plurality of unit cells 400U which are typically arranged two-dimensionally. FIG. 8(b) shows portions of two adjacent unit cells 400U.
The unit cell 400U of a vertical MISFET includes a silicon carbide epitaxial layer 402 formed on the principal surface of a low-resistance n-type SiC substrate 401, a channel layer 407 formed on the silicon carbide epitaxial layer 402, a gate electrode 413 formed on the channel layer 407 with a gate insulating film 411 interposed therebetween, a source electrode 412 in contact with the surface of the silicon carbide epitaxial layer 402, and a drain electrode 414 provided on the reverse surface of the SiC substrate 401.
The silicon carbide epitaxial layer 402 includes a body region (well region) 405 having a conductivity type (herein, p-type) that is different from the conductivity type of the SiC substrate 401, and a drift region 402d formed by a portion of the silicon carbide epitaxial layer 402 where the body region 405 is not formed. The silicon carbide epitaxial layer 402 is an n−-type silicon carbide layer containing an n-type impurity at a lower concentration than the SiC substrate 401, for example. The silicon carbide epitaxial layer 402 is formed by epitaxially growing silicon carbide while supplying a dopant that exhibits the n—type conductivity.
An n+-type source region 416 containing an n-type impurity at a high concentration and a p+-type contact region 409 containing a p-type impurity at a higher concentration than the body region 405 are formed inside the body region 405. The body region 405, the source region 416 and the contact region 409 are formed by a step of implanting an impurity into the silicon carbide epitaxial layer 402, and a high-temperature heat treatment (activation annealing) step of activating the impurity implanted into the silicon carbide epitaxial layer 402. Specifically, a p-type impurity implantation region to be the body region is formed by ion implantation of an impurity (e.g., Al) to be a p-type dopant into the silicon carbide epitaxial layer 402. Then, an n-type impurity implantation region to be the source region and a high-concentration p-type impurity region to be the contact region are formed by ion implantation of an impurity (e.g., nitrogen) to be an n-type dopant and an impurity to be a p-type dopant, respectively, into portions of the p-type impurity implantation region. Then, by performing activation annealing, a source region 408 and the contact region 409 are obtained from the n-type impurity implantation region and the high-concentration p-type impurity region, respectively. A region of the p-type impurity implantation region that is not turned into the source region or the contact region is the body region 405.
The source region 416 and the drift region 402d are connected together via the channel layer 407. The channel layer 407 can be formed by epitaxially growing silicon carbide, while supplying an n-type dopant, on the silicon carbide epitaxial layer 402, for example. Alternatively, it can be formed by implanting ions of an impurity to be an re-type dopant into an epitaxially-grown 4H—SiC layer.
The source electrode 412 forms an ohmic contact with the contact region 409 and the source region 416. Therefore, the body region 405 is electrically connected with the source electrode 412 via the contact region 409. The source electrode 412 can be formed by forming a conductive material (Ni) layer, for example, on the source region 416 and the contact region 409 in the silicon carbide epitaxial layer 402, and then performing a heat treatment at a high temperature.
The gate insulating film 411 is a thermal oxidation film (SiO2 film) formed by thermally oxidizing the surface of the channel layer 407, for example. The gate electrode 413 is formed using conductive polysilicon, for example.
In the SiC-MISFET shown in FIGS. 8(a) and 8(b), a current flow can be conducted through the channel layer 407 which is present under the gate electrode 413 with the gate insulating film 411 interposed therebetween by a voltage applied to the gate electrode 413. Therefore, the current from the drain electrode 414 (the drain current) flows to the source electrode 412 (ON state) through the SiC substrate 401, the drift region 402d, the channel layer 407 and the source region 416.
In an SiC-MISFET, the source electrode is normally an ohmic electrode which is in ohmic contact with the contact region and the source region. For example, Patent Document No. 2 proposes a method for forming an ohmic electrode having a low contact resistance.
On the other hand, Patent Document No. 3 discloses an SiC-MISFET having no source region. FIG. 9 is an enlarged cross-sectional view showing a portion of the SiC-MISFET disclosed in Patent Document No. 3. For the sake of simplicity, like components to those of FIG. 8 are denoted by like reference numerals and will not be described.
The SiC-MISFET shown in FIG. 9 includes, on a silicon carbide epitaxial layer 402, a channel layer 407 having a structure (delta-doped structure) in which δ-doped layers 407b containing an n-type impurity and an undoped layer 407a containing no n-type impurity are alternately layered together. A source electrode (silicide layer) 412 is in contact with the channel layer 407 having a delta-doped structure and a p-type contact region 409.
In this SiC-MISFET, the source electrode 412 is formed by depositing a metal such as nickel on the channel layer 407 and then performing a heat treatment. In this heat treatment, the deposited metal diffuses in the vertical direction (thickness direction) through the channel layer 407. Thus, it is possible to obtain the source electrode 412 which is in contact with the contact region 409.
Patent Document No. 4 discloses a method in which an opening is formed in a channel layer, and an ohmic electrode (source electrode) is formed in the opening (FIG. 7 of Patent Document No. 4).
FIG. 10 is an enlarged cross-sectional view showing a portion of the SiC-MISFET disclosed in Patent Document No. 4. For the sake of simplicity, like components to those of FIG. 8 are denoted by like reference numerals and will not be described.
The SiC-MISFET shown in FIG. 10 is formed as follows. First, a channel layer 407 and an interlayer insulating film 430 are formed on a silicon carbide epitaxial layer 402 including a body region 405 and a source region 416. Then, an opening is formed by etching in the interlayer insulating film 430, the channel layer 407 and the source region 416. An aluminum alloy is deposited in the opening to obtain an ohmic electrode (source electrode) 412 in contact with the source region 416 and the body region 405.